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Description: XILINX的FPGA实现的双口ram源码,可作为dsp\SDRAM和pci桥接作用,可直接使用,实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
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Size: 19456 |
Author: 朱效志 |
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Description: Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and presented on a VGA monitor.zip-Sobel-- Image Filter (I). An Image filteri Vi is made over the data loaded into RAM on board a nd presented on a VGA monitor.zip
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Size: 316416 |
Author: 严刚 |
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Description: 多总线切换的VHDL代码。可用于多RAM的管理。-Multibus VHDL code switching. RAM can be used for multi-management.
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Size: 1024 |
Author: 祝箭 |
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Description: 介绍了viterbi译码器的编解码器的设计,包括decoder.v,encoder.v.control.v,ram.v等,压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
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Size: 62464 |
Author: yaoyongshi |
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Description: 电赛一等奖作品:音频信号分析仪的FPGA源码,VHDL编写,Quartus7.1综合,ModelSim6.2g se仿真,应用了opencores.org上的开源FFT IP核,加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram
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Size: 4933632 |
Author: 李星 |
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Description: 注1: 含有不可综合语句,请自行修改
注2: 一些PLD只允许I/O口对外三态,不支持内部三态,使用时要注意
注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件,并在VHDL程序中例化
-Note 1: contains a comprehensive statement can not, please amend Note 2: Some PLD only permit I/O port of external tri-state, does not support internal tri-state, the use of when we should pay attention Note 3: the design of RAM
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Size: 44032 |
Author: 朱明 |
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Description: 静态随机存储器(SRAM)设计VHDL代码,已经生成的了-Static random access memory (SRAM) design of VHDL code, has generated a
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Size: 345088 |
Author: 陆见风 |
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Description: 学习vhdl硬件描述语言的一些例子的原代码,比较全面,相信对初学者很有帮助-VHDL hardware description language to learn some examples of the original code, a more comprehensive, I believe very helpful for beginners
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Size: 254976 |
Author: 马斌 |
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Description: ad取样,经由cpld处理,存入ram 1000点并由串行的da进行还原-ad sampling, by the CPLD deal, deposited by the serial ram 1000 points to restore the da
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Size: 180224 |
Author: |
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Description: 用vhdl格式写的sram源代码,把扩展名txt改为.v即可-VHDL format used to write the SRAM source code, to be re-txt extension. V can
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Size: 2048 |
Author: 郭艳红 |
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Description: VHDL的ram和fifo model code
包含众多的厂家-VHDL the ram and fifo model code contains a large number of manufacturers
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Size: 1678336 |
Author: SL |
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Description: RAM存储器: 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write= 1 则mem(conv_integer(address))<=datain. -RAM memory: Set 16 8 memory cell. If read = 1 is dataout
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Size: 1024 |
Author: 良芯 |
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Description:
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Size: 10531840 |
Author: liuhongjie |
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Description: 利用vhdl编写的双端口Ram程序,不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction
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Size: 1024 |
Author: 孙敬辉 |
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Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM
实现高速到低速时钟域的数据传输 ,值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
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Size: 928768 |
Author: alison |
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Description: 用双端口ram实现异步fifo,采用格雷码,避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
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Size: 1024 |
Author: shili |
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Description: 用来测试cpu的ram代码 其中包括几十条指令 cpu的vhdl也在本站有下-Cpu the ram used to test the code, including dozens of VHDL cpu instructions also have a website under the
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Size: 1024 |
Author: 闵瑞鑫 |
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Description: 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
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Size: 1024 |
Author: 赵国栋 |
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Description: The Free IP Project
VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core
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Size: 615424 |
Author: cathy |
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Description: xilinx BlockRAM 级联,利用Xilinx原语(非IP Core),更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
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Size: 2048 |
Author: blackmew |
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